Basic VLSI Front End Design Using VHDL | Universal

Basic VLSI Front End Design Using VHDL

Introduction to Digital Electronics

Industry and Design oriented Training
100% Lab orientation.
Exclusive industry Oriented teaching methodology.
Unique and complete study material.

Levels of Testing & It’s Implementation

Introduction to VLSI Design Flow.
Traditional Designing Methods- Designing.
Boolean Equation & Schematic based Design.
Drawback of Traditional Methods.
Designing with HDL.
Different Description Levels of a Design.
Background of Verilog-HDL and VHDL.
Description of Verilog-HDL, VHDL.
Verilog-HDL v/s VHDL.

Basic Concepts of VHDL

Basic VHDL concepts.
Basic terminologies.
Design Entity & Configuration, Generics.
Architecture, Sub Program and Packages.
Identifiers, Data Objects, Data types.
Operators

VHDL modeling techniques

Behavioral Modeling: Declarations.
Process Statements.
Variable Assignment.
Signal Assignment, wait statement.
If, case, loop statement, Inertial Delay.
Transport delay.
Dataflow Modeling
Structural Modeling:

Designing Digital Circuits using Modeling Techniques

Designing of Digital Circuits using Behavioral modeling,
Dataflow modeling and structural modeling.
Writing test bench.

Synthesis

Simulation & Synthesis of various digital circuits.

PROJECT WORK